FIG. 1 is a diagram showing a conventional memory cell array of a NOR-structured mask ROM (often referred to as flat-type mask ROM). Referring to FIG. 1, a first plurality of memory cells, e.g., Mm1 . . . Mm10, is connected in parallel to a second plurality of memory cells, e.g., M11 . . . M20. Each memory cell of the first and second plurality of memory cells is coupled to two adjacent sub bit lines constituting a bank also referred to as a group, a string, etc. The memory cells of each bank are connected to corresponding word lines. For example, the memory cells M11 and Mm1 are connected in parallel between sub bit lines SBL1 and SBL2. The memory cells M11 to Mm1 are also connected to corresponding word lines WL1 to WLm. Each memory cell is composed of a metal-oxide-semiconductor field effect transistor (MOSFET) having a source, a drain and a gate.
In FIG. 1, an even-numbered sub bit line SBL2 is connected to a main bit line MBL1 through an NMOS transistor BST1 (acting as a bank selector). The NMOS transistor BST1 is turned on/off by a select signal SSL1. An even-numbered sub bit line SBL4 is connected to the main bit line MBL1 through an NMOS transistor BST2 (acting as a bank selector). The NMOS transistor BST2 is turned on/off by a select signal SSL2. Other even-numbered sub bit lines SBL6, SBL8, etc., are likewise connected to corresponding main bit lines MBL3, MBL4, etc., through corresponding NMOS bank select transistors BST3, BST4, etc.
An odd-numbered sub bit line SBL1 is connected to a ground bit line GBL1 through an NMOS transistor GST1 (acting as a ground selector). NMOS transistor GST1 is turned on/off by a select signal GSL1. An odd-numbered sub bit line SBL3 is connected to the ground bit line GBL1 through an NMOS transistor GST2 (acting as a ground selector). NMOS transistor GST2 is turned on/off by a select signal GSL2. Other odd-numbered sub bit lines SBL5, SBL7, etc., are likewise connected to corresponding ground bit lines GBL3, GBL4, etc., through ground select transistors GST3, GST4, etc.
The data reading operation of the NOR-structured mask ROM shown in FIG. 1 is as follows. To select a memory cell M11, the select signal SSL1, ground select signal GSL1, and one word line WL1 are activated and the select signal SSL2 and ground select signal GSL2 are deactivated. A main bit line MBL2 adjacent to a selected main bit line MBL1 and a ground bit line GBL1 are grounded. At the same time, the selected main bit line MBL1 is supplied with a sense current Isen through a column pass gate circuit (not shown). The sense current Isen is, in turn, supplied by a prior art sense amplifier 2 shown in FIG. 2. The sense amplifier 2 is disclosed in U. S. Pat. No. 5,856,748, entitled SENSE AMPLIFIER WITH CURRENT MIRROR, incorporated herein by reference.
If the selected memory cell M11 is turned on at the activation of the word line coupled thereto (referred to as an "on-cell"), current supplied to the selected main bit line MBL1 is discharged through a discharge path L1 illustrated by the dotted line. The discharge path L1 comprises the NMOS transistor BST1, the selected memory cell M11, the sub bit line SBL1, the NMOS transistor GST1, and the ground bit line GBL1. Alternatively, if the selected memory cell M11 is turned off at the activation of the word line coupled thereto (referred to as an "off-cell"), the potential of the selected main bit line MBL1 increases because no discharge path L1 is formed. As this happens, the potential of the selected main bit line MBL1 is sensed and amplified by means of the sense amplifier 2. Thus, the memory cells M11, M12, M13, etc., collectively connected to the selected word line WL1 are simultaneously turned on. Leakage current paths to a ground bit line GBL2 and into a main bit line MBL2 may be formed owing to a source-drain voltage difference Vds of memory cells (MOSFETs) commonly connected to the selected word line WL1. The leakage current path is shown as dotted line L2. In particular, when the selected memory cell M11 is an offcell, the leakage current path L2 causes an increased sensing time thereby preventing realization of a high speed mask ROM. Furthermore, in the worst case, even though it is an off-cell, the selected memory cell M11 may be discriminated as the on-cell because the potential of the selected main bit line MBL1 drops owing to the leakage current path L2. Therefore, preventing the formation of the leakage current paths is required to embody a high-speed mask ROM having the NOR structure. One approach for preventing formation of leakage current paths is to make the main bit lines positioned at the right side of a selected main bit line have the same potential as the selected main bit line. The main bit lines having the same potential as the selected main bit line MBL1 are often termed "bias main bit lines". According to the aforementioned approach, no source-drain voltage difference Vds of each memory cell (MOSFET) coupled in common to the selected word line is made. Therefore, the leakage current path L2 is cut off.
The more main bit lines set at the same potential as a selected main bit line, the less current is leaked. The penalty, however, is an increased power consumption and an increased charge/discharge time for charging and discharging a selected main bit line and bias main bit lines. The increased charge/discharge time increases the sensing time thereby preventing realization of a high-speed mask ROM. It also is impossible for only one sense amplifier 2 (FIG. 2) to bias all of the bias main bit lines generating power noise when the bias main bit lines are discharged.